Struct CpuState 

pub struct CpuState {

    pub regs: [u32; 32],
    pub pc: u32,
    pub mstatus: u32,
    pub cyclel: u32,
    pub cycleh: u32,
    pub timerl: u32,
    pub timerh: u32,
    pub timermatchl: u32,
    pub timermatchh: u32,
    pub mscratch: u32,
    pub mtvec: u32,
    pub mie: u32,
    pub mip: u32,
    pub mepc: u32,
    pub mtval: u32,
    pub mcause: u32,
    pub extraflags: u32,
}

Complete architectural state of one RV32IMA hart.

All fields that map directly to ISA registers are pub so that the emulator core in crate::emulator and the MMIO layer in crate::mmio can access them without indirection. Fields that pack multiple logical values (only extraflags) expose typed accessors instead.

Timer fields

The CLINT timer is implemented with four 32-bit fields that form two 64-bit values:

• timerl / timerh — the running mtime counter, incremented by CpuState::tick_timer on every step call.
• timermatchl / timermatchh — the mtimecmp threshold written by the kernel via MMIO. When mtime > mtimecmp, MTIP fires.

Fields

regs: [u32; 32]

General-purpose registers x0–x31. x0 is architecturally zero; the decode loop enforces this by skipping writes when rdid == 0.

pc: u32

Program counter.

mstatus: u32

mstatus CSR.

cyclel: u32

Cycle counter — low 32 bits.

cycleh: u32

Cycle counter — high 32 bits.

timerl: u32

mtime — low 32 bits. Incremented each step by elapsed microseconds.

timerh: u32

mtime — high 32 bits.

timermatchl: u32

mtimecmp — low 32 bits. Written by the kernel via CLINT MMIO.

timermatchh: u32

mtimecmp — high 32 bits.

mscratch: u32

mscratch CSR.

mtvec: u32

mtvec CSR — trap handler base address.

mie: u32

mie CSR — interrupt enable bits.

mip: u32

mip CSR — interrupt pending bits.

mepc: u32

mepc CSR — exception program counter.

mtval: u32

mtval CSR — trap value (faulting address or bad instruction).

mcause: u32

mcause CSR — trap cause code.

extraflags: u32

Packed field — see module-level docs for the bit layout.

Implementations

impl CpuState

pub fn get_privilege(&self) -> u32

Current privilege level: 0 = U-mode, 3 = M-mode.

This emulator only uses M-mode (3) and, when the kernel is running, U-mode (0). S-mode is not implemented.

pub fn set_privilege(&mut self, p: u32)

Set the current privilege level.

pub fn get_wfi(&self) -> bool

Returns true if the CPU is in WFI (Wait-For-Interrupt) sleep.

While sleeping, step returns StepResult::Wfi immediately without executing any instructions. The flag is cleared by tick_timer when MTIP fires.

pub fn set_wfi(&mut self, v: bool)

Set or clear the WFI sleep flag.

pub fn get_reservation(&self) -> u32

Returns the current LR/SC reservation address (RAM offset).

Set by LR.W, consumed and cleared by SC.W.

pub fn set_reservation(&mut self, ofs: u32)

Record a new LR/SC reservation at the given RAM offset.

pub fn get_cycle64(&self) -> u64

Read the full 64-bit cycle counter.

pub fn set_cycle64(&mut self, v: u64)

Write the full 64-bit cycle counter.

pub fn tick_timer(&mut self, elapsed_us: u32)

Advance mtime by elapsed_us microseconds and update MTIP.

Called at the start of every crate::emulator::Emulator::step with the number of microseconds that have passed since the previous call. This keeps the CLINT timer accurate relative to wall-clock time.

MTIP (Machine Timer Interrupt Pending, mip bit 7) is set when mtime > mtimecmp and mtimecmp != 0, and cleared otherwise. Setting MTIP also clears the WFI flag so the CPU wakes up.

pub fn commit_trap(&mut self, trap: Trap, rval: u32, pc: u32) -> u32

Save machine context and redirect the PC to mtvec.

This is the final step of trap handling inside step. It writes the standard trap CSRs and returns the new PC value (always mtvec).

What gets saved

CSR	Value written
mepc	PC of the trapping instruction (PC+4 for interrupts)
mcause	Trap cause code from Trap::to_mcause
mtval	Faulting address (load/store faults) or trapping PC
mstatus	MIE → MPIE, current privilege → MPP, MIE cleared

The privilege mode is set to M-mode (3) regardless of where the trap originated. The kernel’s trap handler is expected to inspect mcause, handle the event, and return with mret.

Trait Implementations

impl Default for CpuState

fn default() -> CpuState

Returns the “default value” for a type.