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Module cpu

riscv_emulator

Module cpu 

Source
Expand description

CPU state, trap handling, and timer logic.

This module defines the complete architectural state of the emulated RV32IMA hart: general-purpose registers, program counter, all machine-mode CSRs, and the CLINT timer counters.

§Key types

  • CpuState — the full register file and CSR set for one hart.
  • Trap — every exception and interrupt cause the CPU can raise.
  • StepResult — what the execution loop returns to its caller.
  • Csr — symbolic names for CSR addresses.

§Design note: extraflags

To stay compatible with the original C implementation, three logical fields are packed into the single extraflags word:

bits [1:0]  — privilege mode  (0 = U-mode, 3 = M-mode)
bit  [2]    — WFI sleep flag
bits [31:3] — LR/SC reservation address (RAM offset >> 3)

Accessor methods (CpuState::get_privilege, CpuState::get_wfi, etc.) hide this packing from the rest of the emulator.

Structs§

CpuState
Complete architectural state of one RV32IMA hart.

Enums§

Csr
CSR addresses used by the emulator.
StepResult
Outcome of a single execution batch (crate::emulator::Emulator::step).
Trap
Trap cause codes, as defined by the RISC-V privileged specification.