Module mmio 

Memory-mapped I/O — peripheral registers and RAM access helpers.

Any address in 0x1000_0000..0x1200_0000 is treated as MMIO. Reads and writes to RAM use ptr::read_unaligned and ptr::write_unaligned to handle unaligned accesses, which are legal in RV32I.

Peripheral map

Address	Peripheral	Notes
0x1000_0000	UART TX/RX	Write = transmit byte; read = receive byte
0x1000_0005	UART LSR	Bit 5 = TX ready, bit 0 = RX ready
0x1100_4000	CLINT mtimecmp low	Written by kernel to schedule next timer IRQ
0x1100_4004	CLINT mtimecmp high
0x1100_BFF8	CLINT mtime low	Read-only; driven by CpuState::tick_timer
0x1100_BFFC	CLINT mtime high
0x1110_0000	SYSCON	0x5555 = poweroff, 0x7777 = restart

UART

The UART is a simplified NS16550-compatible device. TX is always ready (LSR bits 5 and 6 hardwired to 1). RX readiness reflects whether the host has a key waiting in stdin.

In WASM mode, TX bytes are pushed to an output_buf instead of being printed to stdout. This lets EmulatorWasm::step_batch collect output and hand it back to the JavaScript caller.

CLINT

The Core Local Interruptor provides mtime (a free-running 64-bit counter) and mtimecmp (the comparison threshold). When mtime > mtimecmp, MTIP fires. The actual increment happens in CpuState::tick_timer; this module only handles the MMIO read/write interface.

Constants

CLINT_MTIMECMP_HI

CLINT mtimecmp — high 32 bits.

CLINT_MTIMECMP_LO

CLINT mtimecmp — low 32 bits (write-only from software perspective).

CLINT_MTIME_HI

CLINT mtime — high 32 bits (read-only).

CLINT_MTIME_LO

CLINT mtime — low 32 bits (read-only).

SYSCON_ADDR

System controller address. Writing 0x5555 powers off; 0x7777 restarts.

UART_LSR

UART Line Status Register.

UART_TX

UART TX register (write) / RX register (read).

Functions

handle_csr_read

Handle a read from an unrecognized CSR number.

handle_csr_write

Handle a write to an unrecognized CSR number.

handle_load

Handle an MMIO load (read).

handle_store

Handle an MMIO store (write).

is_mmio

Returns true if addr falls in the MMIO region (0x1000_0000..0x1200_0000).

mem_load1

Load 1 byte, zero-extended to 32 bits (LBU).

mem_load2

Load 2 bytes, zero-extended to 32 bits (LHU). Handles unaligned offsets.

mem_load4

Load 4 bytes (LW). Handles unaligned offsets.

mem_load1s

Load 1 byte, sign-extended to 32 bits (LB).

mem_load2s

Load 2 bytes, sign-extended to 32 bits (LH). Handles unaligned offsets.

mem_store1

Store 1 byte (SB).

mem_store2

Store 2 bytes (SH). Handles unaligned offsets.

mem_store4

Store 4 bytes (SW). Handles unaligned offsets.