Hernani Samuel

02 LIVE DEMO — RISCV-EMULATOR LINUX

hernani@dev:~$ ./riscv-emulator --kernel Image READY

RV32I+ Linux WebAssembly // Click BOOT to start the emulator in your browser — no install needed.

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 ██╔══██╗██║╚════██║██║       ╚═══╝╚██╗ ██╔╝
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RV32I EMULATOR · WEBASSEMBLY · LINUX KERNEL

~3.1 MB WASM · runs entirely in your browser

// try these commands

rootno password

system

uname -akernel info

cat /proc/cpuinfoRISC-V CPU info

cat /proc/versionbuild info

dmesg | tailkernel log

memory

free -hmemory usage

cat /proc/meminfodetailed memory

processes

psrunning processes

topprocess monitor

hardware

cat /proc/interruptsCLINT timer & IRQs

ls /binavailable binaries

ls /procproc filesystem

try it

echo "hello from riscv"it just works

./coremarkCoreMark benchmark - takes a few seconds

./hello_linuxhello world binary

./duktapetest fizzbuzz.jsJS engine on RISC-V

busyboxall available commands

03 PROJECTS

hernani@dev:~$ bash projects.sh

❯ status --projects

OK munehisa investment simulator

OK risc-v rv32i emulator

OK brainfuck interpreter

OK chip-8 emulator

CNCL sil compiler — Honorable Mention

❯ info munehisa

Munehisa Investment Simulator COMPLETE

Java 21 · Spring Boot · PostgreSQL · JWT · React · TypeScript · Python · FastAPI · Docker

Full-stack, risk-free investment simulator — create a simulation, pick a historical starting month and base currency, and trade real historical market data month by month against a time-traveling broker. Java 21 / Spring Boot backend with Spring Security, JWT auth, JPA + PostgreSQL (Flyway-migrated schema), and Testcontainers-backed integration tests running in CI. A separate Python/FastAPI service handles market-data fetching; React + TypeScript frontend with an interactive D3 candlestick chart. Deployed live: static frontend on GitHub Pages backed by a Spring Boot API on a Hetzner Cloud VM.

⇗ github.com/HernaniSamuel/munehisa-investment-simulator ⇗ Live Demo ⇗ Screenshots (above)

❯ info riscv

RISC-V Emulator COMPLETE

Rust · WebAssembly

A cycle-accurate RV32IMA emulator written in Rust — boots a real Linux 6.1 kernel and FreeRTOS from bare-metal ELF. Implements the full RV32IMA ISA, machine-mode privileged spec, CLINT timer, UART 16550, ELF loader with symbol table, objdump-compatible disassembler, and execution tracer. Compiles to WebAssembly — see the live demo above, running the kernel in your browser. Inspired by and initially based on CNLohr's mini-rv32ima — the original ~400-line C implementation that first proved the concept of booting Linux on a minimal RV32 core.

⇗ github.com/HernaniSamuel/riscv-emulator ⇗ API Documentation ⇗ Live Demo (above)

❯ info chip-8

CHIP-8 Interpreter COMPLETE

Rust

A Chip-8 interpreter built to learn how virtual machines work, including instruction decoding and ISA concepts.

⇗ github.com/HernaniSamuel/chip8

❯ info brainfuck

Brainfuck Interpreter COMPLETE

Rust

Brainfuck interpreter created to practice software engineering skills and learn Rust, interpreters, and programming language concepts.

⇗ github.com/HernaniSamuel/brainfuck

❯ info sil

SIL SPIR-V Compiler CANCELLED ★ HONORABLE MENTION

Python · ChatGPT

A programming language that compiles to SPIR-V. My first attempt at creating a programming language was intended to rival NVIDIA's CUDA (yes, I didn't really know what I was getting myself into). Never achieved true parallelism, but it actually works on the GPU. An honorable mention for getting this far using pure Python.

⇗ github.com/HernaniSamuel/sil_compiler

❯ █

SOFTWARE
ENGINEER

01 SHOWCASE — MUNEHISA INVESTMENT SIMULATOR

02 LIVE DEMO — RISCV-EMULATOR LINUX

03 PROJECTS

04 ABOUT ME

SOFTWAREENGINEER

01 SHOWCASE — MUNEHISA INVESTMENT SIMULATOR

02 LIVE DEMO — RISCV-EMULATOR LINUX

03 PROJECTS

04 ABOUT ME

SOFTWARE
ENGINEER